1. Field of the Invention
The present invention relates in general to electronic devices and more specifically to a programmable capacitor with minimized gate leakage for use in electronic circuits including phase-locked loops (PLLs) and the like.
2. Description of the Related Art
The transistors implemented using advanced CMOS processes, such as 90-nm (nanometer) CMOS, are exhibiting non-ideal behavioral traits for implementation of the critical analog functions used in various electronic devices, such as current and voltage sources or references, voltage-controlled oscillators (VCOs), charge pumps, filters, etc. Some of these non-ideal transistor traits include increased gate tunneling current, increased drain-source leakage, reduced voltage headroom due to VDD scaling, and increased noise susceptibility due to decreased threshold voltages. The drive to reduce the size of electronic devices has increased the difficulty of implementing capacitors in a semiconductor device. In particular, reducing the thickness of gate oxides increases the gate leakage currents of a capacitor implemented in the semiconductor device. Many functions use a programmable filter with selectable components, such as selectable capacitors, which are digitally selectable using CMOS transistor switches or pass gate switches or the like. The electronic switches tend to leak current when switched off effectively modifying the effective capacitance and compromising intended circuit functionality.
The conventional phase locked loop (PLL) architecture, for example, is not ideal for newer process technologies, does not scale well from one process technology to the next, and must be redesigned for use in various electronic devices in different markets. Furthermore, with respect to PLL design, the very high gain VCOs are causing increased cycle-to-cycle jitter, coupled with increased phase drift due to the ever increasing discrepancy between the internal speed of the processor and the interface reference clock speeds. Modern processors, for example, typically operate in the gigahertz (GHz) range whereas the interface reference clock speeds typically operate in the 16-166 megahertz (MHz) range. Fully digital PLLs can alleviate some of the issues but do not scale very well. Furthermore, the need to integrate more PLLs on chip for System-On-Chip (SOC) applications forces more unique PLL implementations which cause design overhead and risk. The PLL includes a charge pump which generates a control voltage across a filter capacitor, where the control voltage is provided to the VCO for synchronizing frequency and/or phase. It is desired to provide a charge pump with a programmable PLL using electronic switching. Electronic switch gate leakage has compromised programmable filter functionality.
It is desired to provide a programmable filter implemented with newer technologies and for various applications. It is desired to eliminate or otherwise mitigate the effects of gate leakage of electronic devices.